Cyclic redundancy check (CRC) systems confirm that data transferred from a source to a destination was not corrupted during the data transfer. A CRC-enabled device calculates a short, fixed-length binary sequence, known as the check value or CRC, for each block of data to be sent or stored. The CRC is appended to the data block to form a codeword. When a codeword is received or read, the receiving device either compares its check value with one freshly calculated from the data block, or equivalently, performs a CRC on the whole codeword and compares the resulting check value with an expected residue constant. If the check values do not match, then the block contains a data error. Otherwise, the data is assumed to be error-free.
Many CRC codes require the definition of a generator polynomial, which becomes the divisor in a polynomial long division. One feature of a hardware CRC calculation system is a signature generating division polynomial G(x). The polynomials G(x) that are required for CRC calculations are not standardized. For example, different sensor types, such as image sensors and radar, have their own polynomials. Different communication protocols such as universal serial bus (USB), peripheral component interconnect express (PCIe), and ethernet, each have their own polynomial schemes.
CRC systems are either serial implementations, which have a limitation on the throughput per cycle, or parallel implementations with limited polynomial support. This puts severe restrictions on using the CRC hardware accelerator modules for checking data consistency. For example, either the signature generating polynomial is not programmable or the implementation of the CRC system is done as a serial shift register that takes “N” clock cycles to calculate the signature for “N” bit stream.